//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/05/31 10:08:47
// Design Name: 
// Module Name: fp
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module fp(
    input wire clk_100m,
    input wire rst,
    output wire clk_50m
    );
    reg[1:0] count;
    assign clk_50m = count[0];
    always@(posedge clk_100m)
        if(rst == 1)
            count <= 0;
        else 
            count <= count + 1;
endmodule
